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OpenAI’s Jalapeno chip went from first architecture concept to first silicon in under 20 months. Nine months separated the first RTL — register-transfer level code defining the chip’s logic — from tape-out. The team that did it averaged fewer than 100 people across the entire project, a figure that spans system design, software, and supply chain but excludes Broadcom.

Richard Ho, OpenAI’s VP of Hardware, told IEEE Spectrum what drove the pace: internal LLMs fine-tuned for chip design. “The models are giving superpowers to our engineers. Our engineers are still driving the work. They’re still the final arbiter of what’s going on. But they can do things a lot faster. They can explore a lot more paths.”

How the workflow ran

OpenAI built its front-end design workflow around XLS — Accelerated Hardware Synthesis — an open-source high-level synthesis toolchain originally developed at Google. XLS lets chip designers write in DSLX (a domain-specific language inspired by Rust) and C++, which XLS then converts to Verilog. LLMs accelerated the parts of the workflow that exist “in the linguistic domain of the problem,” per Ankur Srivastava, director of semiconductor initiative at the University of Maryland: code generation, verification support, and tasks where understanding language and code together creates leverage.

Broadcom handled the rest. The division was explicit: OpenAI owned end-to-end system design, including the inference accelerator, memory hierarchy, and networking. Broadcom took over “physical design from the gates onward.” Broadcom used OpenAI’s public commercial models throughout, not the internal fine-tuned versions.

Expert read

Three outside chip design experts reviewed the result. Andrew Kahng, distinguished professor at UC San Diego, called OpenAI’s timeline “likely best in class today.” David Chin, co-founder at agentic chip design startup Verkor.io, called the schedule “quite credible” but added that Broadcom’s involvement was essential — without it, the timeline would not have been possible. Ravi Krishna, also at Verkor, called it “a relatively impressive result” and said that with today’s improved LLMs, the same project started now could be completed even faster.

The hardware that came out

Jalapeno, fully unveiled by OpenAI on August 25, delivers 13.4 petaflops of 4-bit compute, 232 gigabytes of memory with 15.4 terabytes-per-second of bandwidth, and up to 3.6x lower end-to-end latency versus Nvidia’s GB300 per OpenAI’s own benchmarks. OpenAI has committed to gigawatt-scale deployment as it moves Jalapeno into its inference fleet.

The chip’s performance is already in the public record. The design story — a sub-100-person team using LLMs to cut a standard 3-4 year tape-out cycle to under two years — is the new addition, and the one most relevant to every hardware team watching what frontier labs are doing with AI-assisted engineering.