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Before any high-bandwidth memory die ships to an AI accelerator, it passes through wafer-testing equipment. That equipment runs on printed circuit boards. And those boards are now 180 layers thick.

In 2025, OKI Circuit Technology — part of Japan’s OKI Group — announced a 124-layer PCB measuring 7.6mm thick, designed specifically for the test jigs used to qualify HBM memory chips headed for AI semiconductor production. In April 2026, OKI extended that work, developing manufacturing processes for 180-layer boards at 15mm thickness — a 45% increase in layer count and roughly double the thickness of its previous generation.

Why Test PCBs Have to Scale With HBM

Conventional server PCBs typically run 12 to 24 layers. Specialized AI server and switch boards push that to 40-plus layers. Test boards are a different category entirely — they do not sit in the final product at all.

HBM packaging requires high-frequency signal integrity across dense interconnects. Each HBM die stacks multiple DRAM layers through through-silicon vias, then connects to the base die and ultimately to the accelerator silicon via microbump arrays. The wafer-testing phase has to probe this structure before the dies are packaged — which means the test PCB must route signals at densities and frequencies that mirror the final product.

As HBM generation count increases (HBM3, HBM3E, HBM4), and as the number of stacks per accelerator rises, the demands on test boards compound. More layers route more simultaneous high-speed channels without crosstalk. The jump from 124 to 180 layers in OKI’s roadmap tracks closely with the progression from HBM3 to HBM4-era production qualification requirements.

The Packaging Chain Behind the Chip

The HBM supply chain is built around three producers — SK Hynix, Samsung, and Micron — and a set of equipment and substrate suppliers that rarely appear in AI infrastructure discussions. OKI sits in the substrate tier of that chain: its test boards are not in the end product, but every chip in the end product passed through them.

This matters for AI infrastructure planning because test capacity is a production ceiling. It is worth noting that HBM stacks themselves are ultimately connected to accelerator silicon in-package via advanced interposers — CoWoS-L in the case of Nvidia’s Blackwell generation — not through server PCBs. But every HBM die must pass wafer-level testing before it reaches packaging. If that test throughput constrains — due to substrate delays, equipment lead times, or layer complexity — it directly limits HBM shipment rates to Nvidia, AMD, and Google’s TPU program.

Current AI server designs already reflect this pressure. PCBs inside AI servers have increased from around 20 layers in standard data center configurations to 40-plus layers in advanced AI accelerator boards, according to industry analyses tracking the generational shift. OKI’s test boards, at 180 layers, represent a ceiling-pushing exercise — developing the substrate technology before production volume demands it.

HBM Market Context

The HBM market is projected to reach $29.65 billion by 2035, driven almost entirely by AI accelerator deployments. SK Hynix, which holds the largest HBM market share and supplies the majority of Nvidia’s HBM allocation, has been expanding packaging capacity and test throughput as its primary production constraint. Micron crossed a record $54.2 billion in fiscal Q4 2026 revenue, with HBM accounting for a growing fraction of its data center mix.

At those volumes, small inefficiencies in test throughput become large numbers at the back end of the supply chain. OKI is among the suppliers developing substrate technology for HBM probe card and test jig equipment. The broader substrate layer — advanced packaging interposers, CoWoS capacity, and the test infrastructure qualifying every HBM die — is where the next set of scaling constraints will appear.