NVIDIA Sets Server-Grade Hardware Requirements for RISC-V CUDA at Hot Chips 2026
CUDA currently supports two CPU architectures: x86-64 and aarch64. NVIDIA is adding a third. At Hot Chips 2026, the company laid out what a RISC-V CPU must provide before CUDA will run on it — and the bar is deliberately high.
The specification starts at the RVA23 profile and requires full compliance with RISC-V’s server SoC and server platform specifications. Those cover RAS features, a security processor, and baseline firmware. On top of that, NVIDIA added three requirements of its own.
PCIe coherency. Without it, DMA engines copying data between CPU and GPU can read stale DRAM values while modified data sits in CPU caches, or the CPU reads stale cache lines after a GPU write. Inserting explicit cache invalidations into the CUDA stack was deemed too complex. RISC-V’s server SoC spec recommends coherency, but NVIDIA is mandating it, not asking for it.
ACPI. NVIDIA’s software relies on ACPI for hardware discovery and power management. RISC-V lacked ACPI support until the UEFI forum standardised it in 2025. The RISC-V BRS specification, ratified last year, now includes ACPI — but wide hardware adoption will lag the standard by several years.
Peer-to-peer PCIe. Without P2P, GPU-to-GPU transfers must route through host memory, adding latency and synchronisation overhead.
NVIDIA also noted an additional set of requirements that fills roughly two pages and was not fully disclosed. Vector extension predication support was cited as one example — it lets the compiler avoid branches and ship tighter kernel code.
Beyond the CPU requirements, NVIDIA briefly covered NVLink Fusion, which lets third-party chipmakers license NVLink IP and connect a custom CPU die to an NVIDIA GPU via NVLink C2C — the same approach used in GB10 with Mediatek. A RISC-V CPU meeting the CUDA requirements would qualify as a NVLink Fusion partner CPU. NVLink Fusion also adds framework-level requirements for DOCA and NCCL.
The practical constraint is significant. Most RISC-V hardware today targets embedded and mid-range server markets. ACPI adoption in particular has historically lagged even in the mature aarch64 ecosystem. NVIDIA expects RISC-V CUDA deployments to be server systems first, not the single-board hardware that dominates current RISC-V volume.
SiFive is the first named partner. A system running CUDA on RISC-V was demonstrated at Hot Chips 2026.
Requirements Checklist
| Requirement | Source |
|---|---|
| RVA23 profile compliance | RISC-V specification |
| Server SoC spec adherence | RISC-V specification |
| ACPI support | UEFI BRS 2025 |
| PCIe cache coherency | NVIDIA-mandated |
| Peer-to-peer PCIe DMA | NVIDIA-mandated |
| Vector extension predication | NVIDIA-mandated |
| DOCA + NCCL frameworks (NVLink Fusion) | NVIDIA-mandated |
The move extends CUDA’s reach to a third ISA at a point when RISC-V is moving aggressively into datacentre compute. Whether it matters near-term depends on how quickly server RISC-V silicon with PCIe coherency ships at volume. NVIDIA is setting the terms now.