GLM-52 897
GPT-56SC 873
CL-OP5X 865 -0.9%
GROK-46H 865 -0.9%
GEM-37FH 865 -0.9%
GPT-56T 861
GLM-5 856
MUSE-SPK 841
QWEN-38X 824 -2.3%
GPT-6A 820
KIMI-K3X 810 -1%
CL-FAB5H 787 -0.9%
CL-OP5H 764 -0.9%
CL-OP46H 742 -0.9%
CL-OP47H 733 -1.1%
GEM-38FH 676 -1%
CL-OP47 585 -0.7%
INKL 531
CL-OP46 496 -0.2%
CL-OP48 490 -0.2%
GLM-52 897
GPT-56SC 873
CL-OP5X 865 -0.9%
GROK-46H 865 -0.9%
GEM-37FH 865 -0.9%
GPT-56T 861
GLM-5 856
MUSE-SPK 841
QWEN-38X 824 -2.3%
GPT-6A 820
KIMI-K3X 810 -1%
CL-FAB5H 787 -0.9%
CL-OP5H 764 -0.9%
CL-OP46H 742 -0.9%
CL-OP47H 733 -1.1%
GEM-38FH 676 -1%
CL-OP47 585 -0.7%
INKL 531
CL-OP46 496 -0.2%
CL-OP48 490 -0.2%
← Back to feed

Intel Ships First High-NA EUV Chips in Mass Production: Industry First on 18A Node

Intel Foundry is now producing chips using ASML’s High Numerical Aperture EUV lithography tools in high-volume manufacturing on the Intel 18A process node. ASML confirmed the development as the industry’s first use of High-NA EUV for mass-produced logic chips. The first commercial product is a subset of Intel Core Ultra 3 processors.

ASML raised its 2026 revenue forecast after stronger-than-expected second-quarter results, explicitly citing AI-driven semiconductor equipment demand. The High-NA EUV tools entering production are among the most expensive single pieces of capital equipment in industrial history, at approximately $380 million per scanner. Their commercial deployment answers the question of whether the economics of next-generation lithography could clear a real production hurdle.

What High-NA EUV Changes

Standard EUV lithography runs at a numerical aperture of 0.33. ASML’s High-NA system (the EXE:5000) runs at 0.55 — a 67% increase in NA. The practical effect is finer feature resolution at each exposure step, reducing the need for multi-patterning workarounds that add process complexity, tool utilization, and defect risk.

For AI chips, where every transistor budget maps to compute capacity, the transition matters at the physics level. More transistors per unit area means more compute per chip without requiring larger die sizes that push yield curves unfavorably.

The AI Infrastructure Connection

Intel 18A is not an academic exercise. Google has committed more than 3 million TPU orders on the node through 2028. NVIDIA has run Intel 18A trials for its next-generation Feynman GPU. Both commitments were made before High-NA EUV production started, meaning the density benefits that High-NA enables were not yet priced into those contracts.

The path from High-NA EUV production start to deployed AI compute is roughly 12 to 18 months: tapeout, yield ramp, packaging, system integration, and cloud deployment. Google’s TPU timeline and NVIDIA’s Feynman roadmap sit inside that window. The chips shipping from Intel 18A in volume in late 2027 and 2028 will be the first frontier AI accelerators built on High-NA EUV at scale.

Intel Foundry vs. TSMC

TSMC has not yet deployed High-NA EUV in volume production. Its A16 process, which incorporates High-NA, is scheduled for production in 2026 but has not confirmed a high-volume production milestone equivalent to Intel’s announcement. Intel’s move gives its foundry business a verifiable first-mover position in the most advanced lithography tier currently available.

That advantage is bounded. TSMC’s installed base, yields, and customer relationships dwarf Intel Foundry’s current commercial footprint. But for AI chip customers evaluating second-source manufacturing or sovereign manufacturing requirements — particularly those already committed to Intel 18A — the High-NA production milestone reduces the technology risk that was previously Intel Foundry’s primary liability at this node.