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Huawei published a technical paper introducing a chip design framework called LogicFolding, built on a concept it calls tau scaling. The paper reframes how progress in semiconductors should be measured: not by transistor size, but by how much signal delay can be removed across the entire compute chain.

The timing is pointed. Jensen Huang, speaking to reporters at Computex in Taiwan this week, said Nvidia has “largely conceded” China’s AI chip market to Huawei. US export restrictions effectively removed Nvidia’s H100 and H20 lines from China, and Huawei’s Ascend hardware has stepped into that vacuum at scale.

What LogicFolding Actually Does

In a conventional chip, related logic gates are distributed across a flat die surface. Signals travel laterally through long resistive metal routes before reaching adjacent circuits. That distance creates delay: wire resistance slows current, parasitic capacitance must be charged and discharged on every transition, and clock timing must account for the jitter introduced by those paths.

LogicFolding addresses this by stacking active circuit layers vertically and connecting them with fine-pitch hybrid bonds. Logic that previously communicated across hundreds of micrometers of flat interconnect now sits directly above and below its counterpart. Signal paths contract. Critical-path timing tightens. Energy per operation falls.

Huawei frames this under a broader concept, tau (the Greek letter denoting delay). Tau scaling asks: where is time being lost? Moore’s Law reduced tau indirectly because smaller transistors also shortened many of the surrounding signal paths. But at advanced nodes, the dominant delay sources are no longer the transistors themselves. They are wire resistance, memory latency, chip-to-chip protocols, and clock distribution. LogicFolding attacks the wire resistance problem directly.

The first implementation is set for Kirin smartphone chips due in fall 2026.

Nvidia’s Admission

Huang’s “largely conceded” comment marks a departure from the public framing Nvidia maintained through most of the export control era. The company had argued that demand would flow to compliant markets and that Chinese customers would eventually face an AI gap severe enough to pressure Beijing into policy changes.

That thesis has not held. DeepSeek’s V4 family ran frontier-class workloads on Ascend 910B hardware at production scale. China’s AI infrastructure buildout, anchored on Huawei silicon, is no longer a second-tier substitution. It is a functioning alternative stack.

Nvidia’s China AI chip revenue was approximately $5B annually before the H20 export ban took effect in April 2025. That revenue is not coming back under current export policy. Huang also told reporters that his forecast for a $200 billion CPU market includes China, signaling that Nvidia’s remaining China exposure sits in non-restricted categories.

The Competitive Arithmetic

Export controls were designed to create a capability gap that compound over time: deny access to the best training chips, and the rival’s model development slows. The assumption was that Huawei could not close the silicon gap without TSMC’s advanced nodes.

LogicFolding complicates that logic. If Huawei can improve performance-per-watt through architectural innovation rather than process node advances, the performance gap narrows on a dimension where export controls have no jurisdiction. The restriction blocks access to 3nm lithography; it does not block access to physics.

The paper’s first use in consumer chips (Kirin) does not mean AI datacenter-grade parts arrive in 2026. But the architectural methodology transfers, and Huawei’s Ascend team has been running on Huawei fabs since the 910A. The same vertical stacking approach that speeds up a smartphone processor speeds up a matrix engine.

Huang’s concession and Huawei’s paper arrived within days of each other. That is not a coincidence in timing; it is a description of the current state of the competition.