CL-SN55 941 —
GPT-61S 885 —
GPT-56T 861 —
GPT-6S 825 —
CL-OP55X 818 -0.1%
MUSE-SPK 793 —
QWEN-38X 779 —
GPT-6A 778 —
CL-OP5H 711 -0.1%
CL-OP5X 709 -0.1%
KIMI-K3X 699 -0.1%
CL-OP46H 694 -0.1%
CL-FAB5H 692 -0.1%
CL-OP55H 692 -0.1%
CL-OP47H 683 -0.1%
GEM-37FH 648 -0.2%
GEM-38FH 633 -0.2%
INKL 531 —
CL-OP47 529 -0.2%
GPT-56S 529 -5.9%
GEM-3P 493 —
CL-OP46 488 —
CL-OP48 481 —
GEM-31P 453 -0.2%
GPT-6L 436 —
CL-SN55 941 —
GPT-61S 885 —
GPT-56T 861 —
GPT-6S 825 —
CL-OP55X 818 -0.1%
MUSE-SPK 793 —
QWEN-38X 779 —
GPT-6A 778 —
CL-OP5H 711 -0.1%
CL-OP5X 709 -0.1%
KIMI-K3X 699 -0.1%
CL-OP46H 694 -0.1%
CL-FAB5H 692 -0.1%
CL-OP55H 692 -0.1%
CL-OP47H 683 -0.1%
GEM-37FH 648 -0.2%
GEM-38FH 633 -0.2%
INKL 531 —
CL-OP47 529 -0.2%
GPT-56S 529 -5.9%
GEM-3P 493 —
CL-OP46 488 —
CL-OP48 481 —
GEM-31P 453 -0.2%
GPT-6L 436 —
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OpenAI and Synopsys Launch GPT-Synopsys to Apply Frontier AI to Semiconductor Design

OpenAI and Synopsys announced a strategic partnership on September 30 to bring frontier AI capabilities into electronic design automation. The product is called GPT-Synopsys.

Synopsys (Nasdaq: SNPS) is the leading vendor in EDA tools, the software used to design, verify, and physically implement semiconductors. Its toolchain sits at every step of the silicon development process, from RTL synthesis through physical design and sign-off. Integrating a frontier language model at that layer has access to engineering data that no AI lab has previously had at scale.

What the Partnership Targets

The stated goal is accelerating the chip design process without degrading PPA outcomes (power, performance, area) or reducing first-time-right silicon rates. Both are the core engineering constraints that drive tape-out risk and schedule overruns. A typical advanced-node chip design cycle runs 18 to 24 months and costs hundreds of millions of dollars before a single wafer is produced.

The announcement describes the integration as combining “OpenAI’s advanced AI capabilities with Synopsys’ industry-leading EDA tools and agentic AI capabilities.” That framing positions GPT-Synopsys as an agentic layer on top of Synopsys’ existing toolchain rather than a replacement for it.

Scope and Stage

Both companies described the partnership as early-stage. No shipping dates, pricing, or benchmark results against existing EDA flows were disclosed in the announcement. Synopsys’ existing AI efforts, including its DSO.ai design space optimisation product, give it an established internal AI practice to integrate against.

Strategic Context

OpenAI’s commercial expansion into industrial verticals has accelerated in 2026. The Synopsys partnership follows an existing silicon collaboration with Broadcom, through which OpenAI co-designed a custom AI inference accelerator that taped out in mid-2026. GPT-Synopsys represents OpenAI entering the EDA software layer rather than simply procuring custom chips. For Synopsys, access to frontier reasoning models could differentiate its toolchain from competitors Cadence and Siemens EDA at a moment when AI-assisted design is becoming a competitive axis.

Both companies explicitly stated that customer chip design data processed through GPT-Synopsys will not be used to train OpenAI’s models and will remain encrypted at rest and in transit.

The commercial terms disclosed include OpenAI licensing Synopsys’ EDA tools under a training subscription and a revenue-sharing framework for customer deployments.