Google Upgrades Taiwan From Chip Supplier to TPU Co-Designer, Expands Shilin R&D by 60%
Google CTO and Senior Vice President of AI Infrastructure Amin Vahdat used his SEMICON Taiwan 2026 opening keynote on September 2 to announce a 60% expansion of the company’s AI infrastructure R&D center in Taipei’s Shilin district, and to reframe the relationship between Google and Taiwanese technology firms.
The language was deliberate. Vahdat described Taiwanese companies as having evolved from “pure manufacturing partners” into “co-design partners,” characterizing the collaboration as “shoulder-to-shoulder” rather than transactional. The distinction matters for how Google’s TPU roadmap is now structured.
What co-design means in practice
Traditional chip supply chain relationships place the fabless designer (Google, in this case) on one side and the foundry and packaging ecosystem on the other. The designer produces the architecture; manufacturers execute it. Co-design flattens that boundary. Taiwanese firms embedded in the process earlier contribute to architecture decisions around interconnects, packaging geometry, and thermal management before tape-out, rather than receiving a completed design to fabricate.
Google has been running an accelerated TPU iteration cycle. The company moved from roughly one generation every three years to a cadence that now approaches two per year. That pace is only sustainable if manufacturing partners are involved in the design loop, not waiting at the end of it. The Shilin expansion is about creating the physical space and institutional capacity to support that level of integration.
The supply chain backdrop
The co-design elevation comes as Google is actively diversifying its chip partnerships. Broadcom holds a design contract through 2031 for TPU architecture work. Samsung and MediaTek were added as partners for the next-generation Icefish TPU, a departure from the previous TSMC-centric model. Fubon projections from August estimated Google is targeting 12 to 15 million TPU v9 chips by 2028, a scale that requires manufacturing partners who are embedded early.
Vahdat’s framing at SEMICON Taiwan positions the island’s technology sector as a structural part of Google’s AI infrastructure strategy, not a commodity supplier. For Taiwanese firms, that means earlier access to design intent and longer-horizon partnerships. For Google, it means reduced iteration time on a chip roadmap where six-month delays have direct consequences for model training timelines.
AI infrastructure demand as the driver
Vahdat noted that AI computing demand is growing exponentially, and that Google’s internal TPU cycle has accelerated in response. The Shilin center expansion is a capital commitment to sustaining that pace in a location that concentrates the packaging, advanced semiconductor, and substrate expertise Google needs closest to the design process.
The 60% expansion figure applies to office space, which tracks headcount growth on the R&D side rather than fabrication capacity. The manufacturing execution still happens at TSMC, Samsung, and partner foundries. What grows in Shilin is the team doing architecture work alongside Taiwanese co-designers.
McKinsey estimated in 2026 that global data center infrastructure will require $6.7 trillion through 2030 to match AI compute demand. Google’s accelerated TPU cadence and deepened Taiwan partnership represent the upstream decisions that will determine whether that infrastructure gets built on time.