Google Adds Marvell as Chip Design Partner for AI Inference — Marvell +6%, Broadcom -2%
Google is in advanced discussions with Marvell Technology to design two new custom AI chips — a memory processing unit (MPU) and an inference-optimized Tensor Processing Unit — in what would be its most significant custom silicon partnership since locking Broadcom into a through-2031 TPU deal earlier this month.
The talks, first reported by The Information and confirmed by CNBC, produced an immediate semiconductor market reaction. Marvell stock gained nearly 6% on Monday. Broadcom fell roughly 2%.
The Two Chips
The first chip is a memory processing unit designed to eliminate the data-movement bottleneck that currently limits throughput during large-scale AI inference. Moving weights and activations between memory and compute is the dominant cost at scale — an MPU addresses this at the silicon level rather than through software optimization.
The second is a dedicated inference TPU, separate from Google’s existing training-focused TPU line. Google split its eighth-generation TPU into two variants at Google Cloud Next this week — TPU 8t for training and TPU 8i for inference — and the Marvell engagement suggests Google wants a purpose-built inference design from a second partner entirely, not just a variant of Broadcom’s training architecture.
The memory chip design could be finalized as early as 2027 before moving into test production, according to reporting from The Information.
Four Partners, One Goal
Google’s custom silicon supply chain now involves four external design partners alongside its own in-house team:
| Partner | Role |
|---|---|
| Broadcom | Primary TPU design, training (extended through 2031) |
| MediaTek | Secondary TPU development |
| Marvell | MPU + new inference TPU (talks ongoing) |
| TSMC | Manufacturing across all designs |
No contract with Marvell has been signed. The Google-Broadcom relationship remains intact — both parties confirmed the 2031 extension weeks ago and Broadcom’s TPU revenue stream is not at risk. What’s changing is that Google is adding capacity and redundancy on the inference side, not replacing anyone.
Why Inference, Why Now
Inference has overtaken training as the dominant cost category for frontier AI labs. Running GPT-5.5, Claude Opus 4.7, or Gemini 3.1 Pro at 900 million weekly users each generates far more continuous compute demand than the one-time training run that created each model. Google’s own estimates put inference TPU capacity as the binding constraint on AI product margins.
Marvell projected its custom compute revenue — what it calls the ASIC business — at $2.5 billion for fiscal 2026, up from effectively zero three years prior. A confirmed Google inference chip deal would materially expand that trajectory. Analysts at Bernstein and Morgan Stanley have flagged the custom compute pipeline as the core driver of the stock’s re-rating.
Nvidia also announced a $2 billion investment in Marvell in March — a strategic move to ensure Nvidia customers can access the ASICs that hyperscalers are building, rather than ceding that ecosystem entirely to Broadcom.
Context: The Custom Silicon Land Grab
Google pioneered the hyperscaler custom chip model with its first TPU in 2015. Amazon, Meta, Microsoft, and OpenAI have all followed since. The logic for each is identical: Nvidia charges premium margins on H100s and GB200s because there is no viable alternative at scale. Custom ASICs break that dependency, but require 18-24 month design cycles and sustained engineering investment.
The custom ASIC market is projected to grow 45% in 2026 and reach $118 billion by 2033. Every major hyperscaler is now running multiple custom chip programs simultaneously, and design partner relationships — not just manufacturing — are becoming a strategic differentiator.
For Marvell, a confirmed Google inference TPU contract would validate its position as the second-most important custom AI chip design house after Broadcom. For Google, it solves a supply-chain concentration problem before it becomes a production problem in 2028 when the next TPU generation needs to ship at full volume.