Alibaba Apsara 2026: Self-Improvement Score Jump Confirmed, Qwen 5 Roadmap at 5-10 Trillion Parameters
Alibaba held its annual Apsara Conference on September 22, 2026 in Hangzhou. Three claims from the event are worth examining: a self-improvement attribution for Qwen3.8-Max, a model scale roadmap, and a new GPU.
The Self-Improvement Claim
Alibaba said Qwen3.8-Max ran 33 automated improvement cycles over approximately one month — spanning pipeline design, data validation, iterative experimentation, and error diagnosis — and that this process raised its Artificial Analysis Intelligence Index score from 40 to 45.
Artificial Analysis independently confirms the score change. Two builds of Qwen3.8-Max appear on the leaderboard: the August 3 release at 40.2 and the September 2 snapshot at 45.4.
| Benchmark | August build | September build |
|---|---|---|
| AA Intelligence Index | 40.2 | 45.4 |
| Terminal-Bench 2.1 | 81.3% | 88.8% |
| Terminal-Bench 4.0 | 18.7% | 38.9% |
| HLE | 43.0% | 43.1% |
| GPQA Diamond | 92.7% | 92.8% |
| Cost to run index (per task) | $2.67 | $5.41 |
The gain is concentrated in Terminal-Bench. HLE, GPQA Diamond, and SciCode barely moved. The cost to run through the index roughly doubled, meaning the model uses more tokens to produce its answers — a signal that extended thinking is doing more work, not that the model has fundamentally improved at the tasks.
Artificial Analysis also changed its index around the same period: version 4.3 added AutomationBench-AA, removed the tau-cubed Banking test, and introduced Terminal-Bench 4.0. The metric with the largest gain from August to September sits on a benchmark the index now weights heavily. Alibaba has published no method, no training logs, no cycle definitions, and no human-oversight details. Whether an automated loop produced the gain, or conventional post-training focused on the same benchmark cluster, is not verifiable from external data.
What the Score Means in Practice
Per-token pricing stayed at $2 input / $6 output across both snapshots. Per-task cost is different. Independent testing published on October 15 found that on hard coding tasks, Qwen3.8-Max uses 19 times more tokens than GPT-5.6 Sol to reach a correct answer. The result: per-task cost of $0.014–$0.028 for Qwen3.8-Max versus $0.007 for GPT-5.6 Sol — 2 to 4 times more expensive despite a 5-times cheaper per-token rate. The model’s completion length on one hard task grew across three consecutive runs (6,104, then 7,752, then 13,965 tokens) while the answer stayed correct. Lower per-token cost and higher per-task cost coexist.
Qwen Roadmap
Alibaba said Qwen 4 is in active training. Qwen 4.5 and Qwen 5 are projected to scale to 5 to 10 trillion parameters. No timeline was given beyond the direction of travel.
At 2.4 trillion parameters, Qwen3.8-Max is already among the largest models deployed in production. A move to 5–10 trillion would represent a 2–4x scale increase and puts Alibaba’s stated trajectory above anything currently deployed. Whether parameter count at that scale produces commensurate capability gains is unresolved.
Zhenwu V900
Alibaba’s chip unit T-Head announced the Zhenwu V900, positioned as the successor to the Zhenwu M890. The stated specs: 3 times the performance of the M890, 216 GB of GPU memory, 1,200 GB per second of inter-chip bandwidth, FP8 and FP4 support. Mass production is targeted for Q1 2027.
The M890 was Alibaba’s previous flagship accelerator. The V900 spec sheet is consistent with a competitive inference chip for large MoE models — 216 GB memory accommodates the active parameter footprint of models in the 95B-active range (like Qwen3.8-Max) without aggressive quantization. Whether the V900 reaches the claimed figures in production and what the volume and export profile looks like are open questions.
Summary
The Apsara announcements fall into two categories: claims with external confirmation (score jump exists, direction of roadmap is consistent with public trajectory) and claims without it (self-improvement attribution, chip performance claims against unnamed baselines). The chip design experiment claim — 10,000 EDA calls, 42% area reduction, zero performance compromise — also lacks a named baseline design or independent validation.
For the model roadmap, the concrete near-term signal is Qwen 4 in training. Everything beyond that is a projected scale target.