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AI is starting to move radio-frequency integrated-circuit design out of template-driven craft work and into direct search. The target is not digital logic, where automated design flows are mature. It is RFICs: the analogue and electromagnetic circuitry that makes phones, satellites, radar systems, wireless sensors, and 5G millimetre-wave devices work.

The reason this matters is simple: RFIC design is still slow, expensive, and heavily dependent on senior human intuition. A new chip can take years and tens to hundreds of millions of dollars because every architecture decision interacts with transistor behaviour, passive electromagnetic structures, thermal constraints, packaging, signal reflection, and manufacturability.

Princeton’s latest work points to a different workflow. Instead of asking a human designer to start from known amplifier or low-noise-amplifier templates, the system begins with specifications and searches the design space directly.

The Stack

The method has two main layers.

First, a reinforcement-learning framework chooses the architecture, topology, device parameters, and electromagnetic interface properties. It is trained like a game-playing system: generate circuit candidates, score them against the target behaviour, and learn which design actions move performance in the right direction. Training takes days to a week. After that, circuit generation is fast.

Second, an inverse-design engine maps desired electromagnetic behaviour into physical layout. RFIC passives are often described by scattering parameters, which capture how signals move through a structure or reflect back. Conventional electromagnetic solvers can take minutes or hours per candidate. Princeton replaced that loop with a convolutional-neural-network emulator trained on large numbers of random pixelated structures and their scattering-parameter labels. Inference drops the electromagnetic prediction step to milliseconds.

That is the practical unlock. The model can explore circuit and layout options at a rate that a conventional simulation loop cannot touch.

The 30-100 GHz Result

The proof point is a millimetre-wave power amplifier spanning 30 to 100 GHz, a range covering major 5G and radar bands. The design produced by the system achieved a leading combination of bandwidth, output power, and efficiency for a silicon-based power amplifier in its class.

The layout did not look like a human RF engineer’s symmetrical template. It looked closer to an arbitrary pixel map. That is the point. The system was not optimising a known human structure. It was searching for an electromagnetic structure that worked.

The same line of work has since extended to multiport integrated circuits, where the difficulty scales fast. A two-port device has four scattering parameters. A four-port device has 16. Prior multiport electromagnetic simulation could require days or weeks of iteration. The newer model evolves candidate structures in minutes.

Diffusion for Debuggable Designs

Purely novel layouts create a second problem: debugging. RF chips need post-fabrication testing, and engineers still need to understand enough of the circuit to diagnose failures.

That is where diffusion models enter. Instead of using text prompts, the system takes desired scattering parameters as input and emits electromagnetic structures as output. A controllable spatial-frequency dial lets designers choose between classical-looking structures, maze-like structures, and highly pixelated ones.

The key number is about 6 minutes from input to layout. The model can generate both strange high-performance structures and more interpretable versions that preserve the same electromagnetic response.

What It Is Not

This is not an LLM sitting in Cadence and typing schematic edits. It is closer to AlphaGo Zero applied to analogue design: search the rule space directly, score candidate moves, and stop inheriting human templates as the starting point.

That distinction matters. The strongest near-term AI engineering gains are showing up where models can sit inside a tight evaluation loop: code tests, protein folding metrics, circuit simulation, chip layout constraints, or robotic reward functions. RFIC design fits that pattern because physics supplies a hard grader.

The remaining bottleneck is data. A general RFIC foundation model would need broad simulation and layout datasets covering circuit behaviour, electromagnetics, process variation, and packaging. That data exists, but most of it is trapped inside company and university silos under nondisclosure agreements.

Open datasets did for computer vision what private image folders could not. RFIC design may need the same shift. Until then, AI can collapse parts of the design loop, but the universal model for analogue and electromagnetic chip design is still blocked by the industry’s least glamorous asset: shared, labelled data.